The Packet Velocity ASIC (PVA) is a hardware acceleration chip that delivers high performance L4 throughput and Denial of Service (DoS) protection.
Full Acceleration (Full)
All traffic is load balanced using Layer 4 features, such as virtual servers that operate only on IP addresses and ports of incoming traffic. The Full acceleration mode is not compatible with Layer 7 features, such as cookie persistence, header insertion, and rules that operate on data payload content.
Partial Acceleration (Assisted)
The first packets in each connection are processed in software, and each packet thereafter is accelerated. This process allows the software to make decisions based on Layer 4 content, but accelerates the traffic once the load balancing or persistence determination has been made.
No Acceleration (None)
No traffic is accelerated.